Advanced packaging: CoWoS, HBM and the memory shortage

Plain English. AI chips are limited by moving data, not doing arithmetic. Advanced packaging is how the industry responds: CoWoS is TSMC's method of mounting compute dies and stacks of high-bandwidth memory (HBM) together on a silicon interposer, so memory sits millimetres from the processor. HBM is that stacked memory.

Why it moves money. This is where chip supply actually bottlenecks — accelerator output is gated by CoWoS and HBM capacity, not raw wafer starts, which is why SK Hynix, Micron and TSMC earnings surprises route through packaging. The shortage arithmetic is stark: Micron states HBM consumes roughly three times the wafer area of DDR5 for the same capacity, and the ratio worsens each generation (reported). The scarcity propagates outward — Nvidia lifting system prices at least 15 per cent on memory costs, desktop CPU shipments down more than 20 per cent as fabs prioritise HBM — making memory the clearest inflation channel in the buildout.

What to watch. CoWoS capacity expansion announcements; HBM supply agreements and prepayments; spot DRAM prices as the early-warning gauge for the whole constraint.

From the signals. Micron puts a number on HBM's cost to everyone else: three times the wafer area. Nvidia to lift prices at least 15% as memory scarcity passes through. Desktop CPU shipments fell over 20% as AI crowds out consumer memory.